The present invention relates generally to integrated circuit (IC) design and, more particularly, to analyzing multiple induced systematic and statistical layout dependent effects on circuit performance.
Yield loss mechanisms in IC manufacturing may generally be categorized into catastrophic (or functional) yield loss mechanisms and parametric yield loss mechanisms, with the latter consisting of both random and systematic components. Catastrophic yield loss refers to defects formed during manufacturing due to local or global process faults such as (for example) oxidation pinholes, mask misalignments, opens or shorts due to incorrect metallization or contamination, etc. Parametric variability, on the other hand, is governed by statistical variation in circuit parameters such as threshold voltage, gate length, oxide thickness, etc. This affects yield loss by leading to circuit performance that does not meet design constraints in terms of timing or power. Significant Design for Manufacturability (DfM) efforts, such as critical area analysis and addition of redundancy, have thus far been focused on analyzing and mitigating catastrophic yield issues.
Technology forecasts show that for 45 nanometer (nm) technology and beyond, parametric uncertainty accounts for an increasingly larger percentage of the total yield loss, with understood systematic parametric variations constituting a significantly high percentage of the same. This increased sensitivity to layout-dependent systematic variations has resulted from competitive chip density needs, which in turn are forcing shapes together that interact in highly complex ways. Certain circuit-level techniques have been used, to good effect, to deal with parameter uncertainty. These techniques have been implemented either at design time using uncertainty aware gate sizing algorithms, or at the post-design tuning stage using adaptive body biasing. Efforts have also been made in timing sign-off with the advent of statistical static timing analysis, however current commercial tools assume cell delays to be normally distributed (an approximation which has been shown to be increasingly inaccurate with each new technology node). While some work has explored the use of non-Gaussian distributions in describing cell delays, results have been mostly conservative in view of the lack of knowledge of the exact nature of delay distributions.
Lithography has long been a primary source of systematic variation, but the impact of variations in dose and defocus on cell delay is not incorporated in extraction. As used herein, integrated circuit extraction or simply “extraction” generally refers to shape processing of the features of a circuit layout in order to determine and assign various electrical parameters corresponding to the design features (i.e., translating the layout back into the electrical circuit or netlist it is intended to represent).
In addition, etching is presently a second studied source of variation, wherein etch rates vary according to different layout configurations. However, current extraction methods do not model the impact of etch rate variations on gate length, and consequently circuit delay.
Contact resistance is still another contributing factor to timing uncertainty in 45 nm and beyond. The impact of contact resistance is measured by mapping the generated contact litho contour to its corresponding device resistance using a three-dimensional truncated cone model. While a conventional extraction does incorporate contact resistance into calculating effective device resistance, variations in contact processing, such as contact dose and defocus, are not taken into account. Consequently, extraction is inaccurate in predicting device resistance at contact processing corners, which are different from the nominal. Finally, a fourth known systematic yield loss mechanism is mechanical stress that is observed as an impact on electron mobility, which in turn is dependent on certain layout parameters such as poly-to-poly spacing, poly-to-N-well boundary spacing, poly-to-contact spacing, etc. Lithographic variations cause these contacts to shift, thus leading to stress variations in the channel.
Accordingly, it would be desirable to be able to implement an improved method of performing integrated circuit extraction in a manner that more robustly accounts for systematic processing variations.